VLSI/CAD Lab

國 立 中 興 大 學

資 訊 科 學 研 究 所

電 腦 輔 助 設 計

Computer-Aided Design of Digital Systems

Spring 1998

Hours:      Lecture Th 9: 10-12:00 a.m.

                Office W 4:00-5:00 p.m.

Instructor: Sying-Jyan Wang

                Office: 910

                Tel: 2840497-910

Prerequisites:    You are assumed to be familiar with the following topics.

                · Concepts in logic design

                · Elementary Graph Theory

                The course is self contained.

Reading :   The following texts are recommended but not required.

                High-Level Synthesis, D. D. Gajski, N. Dutt, A. Wu, and S. Lin.

                Logic Minimization Algorithms for VLSI Synthesis, R. K. Brayton, G. D.

                Hachtel, C. T. McMullen, and A. Sangiovanni-Vincentelli.

                Design Systems for VLSI Circuits, G. De Micheli, A. Sangiovanni-Vincentelli,

                and P. Antognetti (editors).

                Physical Design Automation of VLSI Systems, B. Preas and M. Lorenzetti

                (editors).

                More advanced materials regarding hardware/software codesign and high-level synthesis will be given in class.

                The following book is a good starting for the use of CAD tools as well as

                some ABC's about CAD tools. Too simple for graduate level, though.

                Contemporary Logic Design, R. H. Katz.

                The following books are for Verilog.

                Digital Design and Synthesis with Verilog HDL, E. Sternheim , R. Singh, R.

                Madhavan, and Y. Trivedi. 台北圖書公司

                Manuals from CIC and Synopsis.

Requirements:   · Homework. The homework includes regular pencil-and-paper assignments which deal with techniques used in tool design, and computer work which deals with the use of tools in real design.

        · Two tests. Each test has the same weight as a homework.

        · Final Project. The final project will be an independent work for each student.

Grading:   The required work will be weighted as follows:

Homework + 2 Tests: 70%

Project:    30%

                The weighs on exams and project may be changed.

Syllabus

This course intends to cover both the theoretical and practical aspects of the current CAD system. The emphasis will be given to the introduction of techniques used in design tools for VLSI design; however, the use of tools for actual designs will be addressed. The emphasis will be on the fundamental techniques used in various aspects of automating the design process. In addition, future trends in this area will be pointed out.

This course will cover the following topics.

Design Synthesis

· Hardware/Software Codesign

· Hardware-Description Language (HDL) -- Verilog

· High-Level Synthesis

    - Design Description       

    - Partitioning

    - Scheduling

    - Resource Allocation

· Logic Synthesis

    - Two-Level Logic Synthesis   

    - Multi-Level Logic Synthesis

    - Technology Mapping

· Physical Synthesis

     - Layout styles

    - Partitioning

    - Array layout

    - Symbolic layout and compaction

    - Place and route

    - Floorplanning

Design Analysis

· Physical analysis

    - Design rule checking (DRC)

    - Connectivity checking

· Functional Analysis

    - Gate and switch-level timing analysis

    - Gate and switch-level logic analysis

            1. Simulation

            2. Verification

Design Management

· Data management

· Tool integration

國 立 中 興 大 學

資 訊 科 學 研 究 所

數 位 系 統 測 試

Digital System Testing

Spring 1999

Hours:       Lecture W 1:10-4:00 p.m.

                Office W 4:00-5:00 p.m.

Instructor:   Sying-Jyan Wang

                Office: 910

                Tel: 2840497-910

Prerequisites:    You are assumed to be familiar with the following topics.

                · Concepts in logic design

                · Theory of switching and sequential systems

Reading :    Text:

        Digital Systems Testing and Testable Design, M. Abramovici, M. A. Breuer,                 and A. D. Friedman.

                Testing and Reliable Design of CMOS Circuits, N. K. Jha and S. Kundu.

                IDDQ Testing of VLSI Circuits, R. K. Gulati, et al.

        We will cover most part of the first text, and part of the second one. The third               one is the only book published so far on the topic of IDDQ testing. We will               cover some of the topics in it. Our library has one copy of the book.

                Reference Books:

    Fault-Tolerant Computing: Theory and Techniques, D. K. Pradhan (editor).

    More advanced material and more depth in every aspects.

        Test Generation for VLSI Chips: Tutorial, V. D. Agrawal and S. C. Seth. This tutorial includes most classic papers in testing. We have one in library.

Requirements:   · Home work. There will be an assignment every 2-3 week, and you have two weeks for each assignment. 20% will be deducted each working day if you turn in the assignment after the due day.

        · Two exams.

        · Final Project. The final project will be an independent work for each student. The topic of the project can be anything covered in the class, with the approval from the instructor. We will discuss this in more detail as the course proceeds.

Grading:    The required work will be weighted as follows:

Home work: 20%

Mid Term: 20%

Final: 30%

Project:    30%

        The weighs on exams and project may be changed.

Syllabus

The course introduces the techniques employed in testing, design for testability and fault-tolerant design of digital systems. We will cover the following topics.

1. Basic concepts of reliability

· Reliability and the failure rate

· Mean-time-between-failures

· Maintainability and availability

2. Fault Models

· Stuck-at faults

· Bridging faults

· Stuck-open and stuck-on faults for MOS circuits

· Delay faults

· Temporary faults

3. Test generation

· Fault simulation

· Test generation for combinational circuits

    - D-algorithm

    - PODEM

· Detection of multiple faults

· Testing of CMOS circuits

    - Logic testing

    - IDDQ Testing

· Functional testing

· Memory testing

· Delay fault testing (optional)

4. Design for testability

· Ad hoc design for testability techniques

· Scan design

· Boundary-scan and IEEE 1149.1

· Built-in self-test

    - Testing methodology

    - Linear Feedback Shift Register (LFSR)

  - Pseudorandom testing

5. Coding theory for fault-tolerant systems

· Parity check codes

· Unidirectional error detecting codes

· Codes for memory

· Arithmetic codes

6. Self-checking design

· Self-checking circuits

· Self-checking checkers

7. System-level diagnosis

· PMC model

· Diagnosis and diagnosibility

8. Topic of interest

· Embedded-IP testing

· FPGA testing