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C.-C. Wang and S.-J. Wang, “A new expander design for a wideband switching system,” in
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[81級 王啟信]
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C.-C. Wang and S.-J. Wang, “Reducing test cost of sequential machines with lower hardware overhead,” in
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[81級 王啟信]
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P.C. Hsu and S.-J. Wang, “Testing and diagnosis of board interconnects in microprocessor-based systems,” in
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[83級 許博清]
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S.-J. Wang and M.-D. Horng, “State assignment for lower power consumption in sequential circuitst,” in
Proc. Int’l Conf. on Computer Architecture
(ICS’96), pp. 210-217, Kaohsiung, Taiwan, 1996.
[83級 洪明德]
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S.-J. Wang and T.-M. Tsai, “Tset and diagnosis of faulty logic blocks in FPGAs,” in
Proc. Int’l Conf. on Computer-Aided Design
, pp.722-727, San Jose, CA, USA, 1997.
[84級 蔡志銘]
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S.-J. Wang, J.-F. Yu, and C.-H. Ko, “Testing interconnect faults in core-based systems,” in
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[84級 于傑芳]
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S.-J. Wang and C.-N. Huang, “Testing and diagnosis of interconnect structures in FPGAs,” in
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Asian Test Symposium
, pp 283-287, Singapore, Nov. 1998.
[85級 黃照能]
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C.-Z. Yung and S.-J. Wang, “Behavioral synthesis-for-testability for conditional statements with multiple branches,” in
Proc. Workshop on Computer Architecture, ICS’98
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[85級 楊中仁]
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W. Lin and S.-J. Wang, “NSC98 Bus Interface Unit,”
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S.-J. Wang and C.-J. Wei, “Efficient built-in self-test algorithm for memory,” in
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Asian Test Symposium
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[86級 魏震榮]
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S.-J. Wang and S.-N. Chiou, “Generating efficient tests for continuous scan,” in
Proc. Design Automation Conf.
, pp. 162-165, Las Vegas, Nevada, USA, June 2001.
[87級 邱升南]
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P.-C. Tsai and S.-J. Wang, “An FSM-based programmable memory BIST architecture,” in
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Workshop on Register Transfer Level Automatic Test Pattern Generation & Design for Testability
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[89級 蔡栢樟]
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S.-J. Wang and Y.-H. Lin, “An adjustable BIST TPG design for low-power testing,” in
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[88級 林燕宏]
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Y.-L. Hsu and S.-J. Wang, “Retiming-based logic synthesis for low-power,” in
Proc. Int’l Symp. Low Power Electronics and Devices
(ISLPED), pp. 275-278, Montery, CA USA., 2002.
[88級 徐玉龍]
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N.-C. Lai and S.-J. Wang, “A Reseeding Technique for LFSR-Based BIST Applications,” in
Proc.
11
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Asian Test Symposium
, pp. 200-204, Nov. 2002.
[91級 賴南成]
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C.-F. Huang and S.-J. Wang, “Design of Low-Cost Self-Checking Circuits,” in
Proc. Int’l Computer Symp
., Dec. 2002.
[89級 黃建峰]
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P.-C. Tsai and S.-J. Wang, “Test Pattern Reordering for Low-Power Testing,” in
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[89級 蔡栢樟]
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P.-C. Tsai and S.-J. Wang, “Test Generation and Compaction for Continuous Scan,” in
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[89級 蔡栢樟]
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N.-C. Lai and S.-J. Wang, “Low Power BIST with Smoother,” in
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13
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Asian Test Symposium
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N.-C. Lai and S.-J. Wang, “Low Power BIST with Smoother,” in
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Y.-H. Fu and S.-J. Wang, “Test Data Compression with LFSR-Reseeding and Seed Overlapping,” in
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[91級 傅煜烜]
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P.-C. Tsai and S.-J. Wang, “Test Data Compression for Minimum Test Application Time,” in
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[89級 蔡栢樟]
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P.-C. Tsai, S.-J. Wang, and F.-M. Chang, “FSM-Based Programmable Memory BIST with Macro Command,” in
Proc. IEEE Int’l Workshop on Memory Technology, Design, and Testing
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[89級 蔡栢樟
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M.-C. Wen; S.-J. Wang, and Y.-N. Lin, “Low Power Parallel Multiplier with Column Bypassing,” in Proc. IEEE Int’l Symp. on
Circuits and Systems, Vol. 2, pp. 1638-1641, Kobe, Japan, 2005.
[91級 溫明振]
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Y.-H. Fu and S.-J. Wang, “Test Data Compression with Partial LFSR-Reseeding,” in
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Asian Test Symp
., Kolkata, India, Dec. 2005.
[91級 傅煜烜]
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F.-M. Chang and S.-J. Wang, “Interconnect-Aware High-Level Synthesis and Floorplaning,” in
Proc
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., Aug. 2005.
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T.-H. Yeh and S.-J. Wang, “
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[93級 葉東樺]
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S.-J. Wang, K.-L. Peng, and K. S.-M. Li, “Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage,” in
Proc. Asian Test Symp.
, Fukuoka, Japan, pp. 169-174, Nov. 2006.
[93級 彭國霖]
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B.-J. Tsai and S.-J. Wang, “Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and
Test Time Reduction,” in
Proc. Asian Test Symp.
, Fukuoka, Japan, pp. 225-230, Nov. 2006.
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S.-J. Wang and T.-H. Yeh, “
High-Level Test Synthesis for Delay Fault Testability
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[93級 葉東樺]
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S.-J. Wang, Y.T. Chen, and K. S.-M. Li, “Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on
Don’t-Care Filling,” in
Proc. Int’l Symp. on Circuit and System
, New Orleans, USA, pp. 27-30, May 2007.
[93級 陳彥廷]
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N.-C. Lai and S.-J. Wang, “Low-Capture-Power Test Generation by Specifying Minimum Set of Controlling Inputs,” in
Proc. Asian Test Symp.
, pp. 413-418, Oct. 2007.
[91級 賴南成]
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S.-J. Wang, X.-L. Li, and K. S.-M. Li, “Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis,” in
Proc.
Asian Test Symp.
, pp. 129-132, Oct. 2007.
[93級 李信龍]
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S.-J. Wang, P.-C. Tsai, H.-M. Weng, and K. S.-M. Li, “Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode
Segmented Scan Architecture,” in
Proc. Asian Test Symp.
, pp. 95-98, Oct. 2007.
[89級 蔡栢樟]
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S.-J. Wang, S.-C. Chen, and K. S.-M. Li, “Design and Analysis of Skewed-Distribution Scan Chain Partition for Improved Test
Data Compression,” in
Proc. Int’l Symp. on Circuit and System
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[94級 陳世政]
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N.-C. Lai and S.-J. Wang, “On-Chip Test Generation Mechanism for Scan-Based Two-Pattern Tests,” in
Proc. Asian Test Symp.
, Sapporo, Japan, pp. 251-256, Nov. 2008.
[91級 賴南成]
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S.-J. Wang, S.-J. Huang, and K. S.-M. Li, “Static and Dynamic Test Power Reduction in Scan-Based Testing,” in
Proc. Int’l Symp. on VLSI Design, Automation, and Test
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[95級 黃順傑]
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K. S.-M. Li, M.-H. Hsieh, and S.-J. Wang, “Level Converting Scan Flip-Flops,” in
Proc. Int’l Symp. on Circuit and System
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[95級 許槐煙]
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S.-J. Wang, K.-L. Fu, and K. S.-M. Li, “Low Peak Power ATPG and Test Compactionfor n-Detection Test,” in
Proc. Int’l Symp. on Circuit and System
, June 2009.
[95級 傅國霖]
-
C.-C. Wang, J.-W. Liu, R.-C. Kuo, K. S.-M. Li, and S.-J. Wang, “A 1.8 V to 3.3 V Level-Converting Flip-Flop Design for Multiple
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[81級 王啟信]
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T.-H. Tzeng and S.-J. Wang, “Fast and Accurate Statistical Static Timing Analysis,” in
Proc
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[96級 曾琮暉]
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T.-H. Yeh and S.-J Wang "Thermal Safe High Level Test Synthesis for Hierarchical Testability", in
Proc. Asain Test Symp.
, Dec., 2010.
[93級 葉東樺]
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T.-H. Yeh, S.-J Wang, and
K. S.-M. Li
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[93級 葉東樺]
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