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碩士論文 |
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82級
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Reducing Test Cost of Sequential
Machines with Lower Hardware Overhead
[王啟信]
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83級
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The Test Generation and Compaction for
Multiple Fault Models in Combinational Circuits
[許志銘]
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84級
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Testing and Diagnosis of Interconnection
Faults in Microprocessor-Based System
[許博清]
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State Assignment for Low Power Consumption in Sequential Circuits
[洪明德]
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85級
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IDDQ Testing: A Backtracking Method to Generate Complete Test Patterns for Leakage Faults
[吳志偉]
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Analyzation and Testing of Interconnect Faults in Microprocessor-Based Systems
[柯健華]
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Simulation of Interconnection Faults in Microprocessor-Based System
[于傑芳]
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Test and Diagnosis of Faulty Logic Blocks in FPGAs
[蔡志銘]
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86級 |
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By Modifying Behavioral Description To Improve Testability Problem Caused By Conditional Statement
[楊中仁]
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Test and Diagnosis of Interconnect in FPGAs
[黃照能]
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Modifying User-Defined Logic for Testing Embeded Core [王弘儒]
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87級 |
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Controlling ATPG To Improve Testability Problem Caused By Multiple-Branch
[連家駿]
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BIST-Based Diagnosis of Interconnect Faults in FPGAs
[李國恩]
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Functional Verification Based on Binary Decision Diagram
[江政翰]
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Multiple-Branch Testable Design
[陳瑞峰]
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Built-In-Self-Test for Embedded Memories
[魏震榮]
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88級 |
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Generating Efficient Tests for
Continuous Scan [邱升南] |
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Built-In Self-Repair Design
[莊舜如] |
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The Design and Analysis of the
All-Digital CMOS Delay-Locked Loop [黃嘉慶] |
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ARM8 Core Design and Verification
[吳志恆] |
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89級
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Low Power Built In Self Test
Design [林燕宏] |
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Structural Precomputation Design
for Low Power [徐玉龍] |
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Reducing Test Application Time
for Logic-BIST [陳啟民] |
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90級 |
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Structural Precomputation Design
for Low-Power Logic Synthesis [王瑛嘉] |
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Lower Hardware Redundancy TSC for
Finite State Machine Output Using Berger Code
[陳勁興] |
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A Current Error Detection Method
Based on Addition and Subtraction Operations
[黃建峰] |
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A Study on the Selection of
LFSR's Characteristic Polynomial [劉威廷] |
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A Reseeding Technique for LFSR-Based
BIST Applications [賴南成]
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91級
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An Integrated High Level
Synthesis Method : Scheduling and Resource Allocation for Low Power
[周志霖] |
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92級 |
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Low power Multiplier with Column
Bypassing [溫明振] |
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Simultaneously Reduce Average
Power and Peak Power During Behavioral Synthesis : Using
Efficient Shared Operation
[葉東樺]
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High Level Synthesis for Low
Power and Testability [鄭嘉文] |